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esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 1/12 high input voltage, low quiescent current, low-dropout linear regulator general description the emp8040 is a high voltage, low quiescent current, low dropout regulator with 100ma output driving capacity. the emp8040, which operates over an input range of 3v to 36v, is stable with any capacitors, whose capacitance is larger than 1 f, and suitable for powering battery-management ics because of the virtue of its low quiescent current consumption and low dropout voltage. emp8040 also includes bandgap voltage reference, constant current limiting and thermal overload protection. applications g logic supply for high voltage batteries g keep-alive supply g 3-4 cell li-ion batteries powered systems features g 100ma guaranteed output current g 500mv typical dropout at io=100ma g 10a typical quiescent current g 1a typical shutdown mode g 3.0v to 36v input range g stable with small ceramic output capacitors (1f) g over temperature and over current protection g 2.5% output voltage tolerance typical application v in v out adj 15 4 v in 1 f v out emp8040 en 3 gnd 2 i gnd 1 f r2 r1 vref 2 r 1 r 1 v out ? ? ? ? ? ? ? + =
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 2/12 connection diagrams order information emp8040-xxvf05nrr xx output voltage vf05 sot-23-5 package nrr rohs & halogen free package rating: -40 to 85c package in tape & reel order, marking & packing information package vout product id. marking packing sot-23-5 adj EMP8040-00VF05NRR tape & reel 3kpcs pin functions name sot-23-5 function v in 1 supply voltage input require a minimum input capacitor of close to 1f to ensure stability and sufficient decoupling from the ground pin. gnd 2 ground pin en 3 shutdown input set the regulator into the disable mode by pulling the en pin low. to keep the regulator on during normal operation, force this pin > 1v. once the forcing voltage > 6v, there will be several micro-ampere leaking current. adj 4 adjust: feedback input. connect to resistive voltage-divider network. v out 5 output voltage
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 3/12 functional block diagram fig.1. functional block diagram of emp8040
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 4/12 absolute maximum ratings (notes 1, 2) v in , en -0.3v to 40v v out -0.3v to 13.2v power dissipation (note 3) storage temperature range -65c to 150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec.) 260c esd rating human body model 2kv operating ratings (note 1, 2) supply voltage 3.0v to 36v operating temperature range -40c to 85c thermal resistance ( ja ) sot-23-5 152c /w thermal resistance ( jc , note 3)) sot-23-5 81c/w electrical characteristics t a = 25c, v out (nom)=5v; unless otherwise specified, all limits guaranteed for v in = v out +1v, en = 2v, c in = c out =1f. symbol parameter conditions min typ (note4) max units v in input voltage 3.0 36 v v otl output voltage tolerance 0.1ma i out 100ma v out (nom) +1v v in 36v -2.5 +2.5 % of v out (nom) vref reference voltage 1.176 1.2 1.224 v i out maximum output current average dc current rating 100 ma i limit output current limit 600 ma i out = 0.1ma 10 supply current i out = 100ma 50 i q shutdown supply current v out = 0v, en = gnd 1 a i out = 30ma 135 v do dropout voltage v out =5.0v (note. 5) i out = 100ma 500 mv line regulation i out = 1ma, (v out + 1v) v in 36v 0.1 % v out load regulation 0.1ma i out 100ma 0.5 % e n output voltage noise i out =10ma,10hz f 100khz v out = 5.0v 800 v rms v ih , (v out + 1v) v in 36v 1.0 v en en input threshold v il , (v out + 1v) v in 36v 0.3 v en = gnd or v in (v in <6v) 0.1 i en en input bias current en = v in (36v>v in >6v) 35 a thermal shutdown temperature 150 t sd thermal shutdown hysteresis 30 t on start-up time c out = 1.0f, v out at 90% of final value 500 s
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 5/12 note 1: absolute maximum ratings indicate limits beyond which damage may occur. electrical specifications do not apply when operating the device outside of its rated operating conditions. note 2: all voltages are with respect to the potential at the ground pin. note 3: maximum power dissipation for the device is ca lculated using the following equations: ja a j d t - (max) t p = where t j (max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction-to-ambient thermal resistance. e.g. for the sot-23-5 package ja = 152c/w, t j (max) = 150c and using t a = 25c, the maximum power dissipation is found to be 822mw. the derating factor (-1/ ja ) = -6.57mw/c, thus below 25c the power dissipation fi gure can be increased by 6.57mw per degree, and similarity decreased by this factor for temperatures above 25c. z jc represents the resistance between the chip and the top of the package case. note 4: typical values represent the most likely parametric norm note 5: dropout voltage is measured by reducing v in until v out drops to 98% its nominal value.
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 6/12 typical performance characteristics unless otherwise specified, v in = v out (nom) + 1v, v out =5v, c in = c out = 1.0f, t a = 25c, en = 2v psrr vs. frequency (v in =6v, v out =5v) dropout voltage vs. load current (v out =5.0v) frequency (hz) t 10 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k -70 -60 -50 -40 -30 -20 -10 0 psrr(db) 1ma 10ma 30ma 50ma vout=5v 0mv 100mv 200mv 300mv 400mv 500mv 600mv 700mv 0ma 20ma 40ma 60ma 80ma 100m a iout dropout voltage 25 -40 85 dropout voltage vs. temp (v out =5.0v) ground current vs. iout (v out =5.0v) 0mv 100mv 200mv 300mv 400mv 500mv 600mv 700mv -45 -30 -15 0 15 30 45 60 75 90 tem p erature dropout voltage 30ma 100ma 0ua 10ua 20ua 30ua 40ua 50ua 60ua 0ma 20ma 40ma 60ma 80ma 100m a iout ign d 25 -40 85 ground current vs. v in (v out =5.0v) v out vs. iout (v out =5.05v) 8ua 9ua 10ua 11ua 12ua 13ua 14ua 15ua 6v 8v 10v 12v 14v 16v 18v 20v 22v 24 v v in ignd 25 -40 85 4.80v 4.85v 4.90v 4.95v 5.00v 5.05v 5.10v 5.15v 5.20v 0ma 20ma 40ma 60ma 80ma 100m a iout vout 25 -40 85
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 7/12 typical performance characteristics (cont.) unless otherwise specified, v in = v out (nom) + 1v, v out =5v, c in = c out = 1.0f, t a = 25c, en = 2v enable response (v out =5.0v, iout=0.1ma) enable response (v out =5.0v, iout=30ma) ~400us ven (0.5v/div) vout (1.0v/div) time (200us/div) ~400us ven (0.5v/div) vout (1.0v/div) time (200us/div) line transient (iout=1ma) line transient (iout=30ma) vin (1v/div) vout (20mv/div) time (100us/div) vin (1v/div) vout (50mv/div) time (100us/div) load transient (v out =5.0v) load transient (v out =5.0v) vout (50mv/div) iout (10ma/div) time (100us/div) vout (200mv/div) iout (50ma/div) time (100us/div)
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 8/12 application information general description referring to fig.1 as shown in the functional block diagram section, the emp8040 adopts the classical regulator topology in which negative feedback control is used to perform the desired voltage regulating function. the negative feedback is formed by using feedback resistors (r1, r2) to sample the output voltage for the non-inverting input of the error amplifier, whose invertin g input is set to the bandgap reference voltage. by the virtue of its high open-loop gain, the error amplifier operates to ensure that the sampled output feedback voltage at its non-inverting input is virtually eq ual to the preset bandgap reference voltage. the error amplifier compares the voltage difference at its inputs and produces an appropriate driving voltage to the p-channel mos pass transistor to control the amount of current reaching the output. if there are changes in the output voltage due to load changes, the feedback resistors regist er such changes to the non-inverting input of the error amplifier. the error amplif ier then adjusts its driving voltage to maintain virtual short between its two input nodes under all loading conditions. in a nutshell, the regulation of the output voltage is achieved as a direct result of the error am plifier keeping its input voltages equal. this negative feedback control topology is further augmented by th e shutdown, the fault detection, and the temperature and current protection circuitry. output capacitor the emp8040 is specially designed for use with ceramic output capacitors of as low as 1.0f to take advantage of the savings in cost and space as we ll as the superior filtering of high frequency noise. capacitors of higher value or other types may be used, but it is important to make sure its equivalent series resistance (esr) is restricted to less than 0.5 ? . the use of larger capacitors with smaller esr values is desirable for applications involving large and fast input or output transients, as well as for situations where the application systems are not physically located immediately adjacent to the battery power source. typical ceramic capacitors suitable for use with the emp8040 are x5r and x7r. the x5r and the x7r capacitors are able to maintain their capacitance values to within 20% and 10%, respectively, as the temperature increases. no-load stability the emp8040 is capable of stable operation during no-load conditions, a mandatory feature for some applications such as cmos ram keep-alive operations. input capacitor a minimum input capacitance of 1f is required for emp8040. the capacitor value may be increased without limit. improper workbench set-ups may have adverse effects on the normal operation of the regulator. a case in point is the instability that may result from long supply lead inductance coupling to the output through the gate capacitance of the pass transistor. this will esta blish a pseudo lcr network, and is likely to happen under high current conditions or near dropout. a 10f tantalum input capacitor will dampen the parasitic lcr action thanks to its high esr. however, cautions should be exercised to avoid regulator short-circuit damage when tantalum capacitors are used, for they are prone to fail in short-circuit operating conditions.
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 9/12 power dissipation and thermal shutdown thermal overload results from excessive power dissipation that causes the ic junction temperature to increase beyond a safe operating level. the emp8040 relies on dedicated thermal shutdown circuitry to limit its total power dissipation. an ic junction temperature t j exceeding 150c will trigger the thermal shutdown logic, turning off the p-channel mos pass transistor. the pass transistor turns on again after the junction cools off by about 30c. when continuous thermal overload conditions persist, this thermal shutdown action then results in a pulsed waveform at the output of the regulator. the concept of thermal resistance ja (c/w) is often used to describe an ic junction?s relative readiness in allowing its thermal energy to dissipate to its ambient air. an ic junction with a low thermal resistance is preferred becaus e it is relatively effective in dissipating its thermal energy to its ambient, thus resulting in a relatively low and desirable junction temperature. the relationship between ja and t j is as follows: t j = ja x (p d ) + t a t a is the ambient temperature, and p d is the power generated by the ic and can be written as: p d = i out (v in - v out ) as the above equations show, it is desirable to work with ics whose ja values are small such that t j does not increase strongly with p d . to avoid thermally overloading the emp80 40, refrain from exceeding the absolute maximum junction temperature rating of 150c under continuous operating conditions. overstressing the regulator with high loading currents and elevated input-to -output differential voltages can increase the ic die temperature significantly. shutdown the emp8040 enters the sleep mode when the en pin is low. when this occurs, the pass transistor, the error amplifier, and the biasing circuits, including the bandga p reference, are turned off, thus reducing the supply current to typically 1a. such a low supply current makes the emp8040 best suited for battery-powered applications. the maximum guaranteed voltage at the en pin for the sleep mode to take effect is 0.3v. a minimum guaranteed voltage of 1.0v at the en pin will ac tivate the emp8040. direct connection of the en pin to the v in to keep the regulator on is allowed for the emp8 040, but there will be several micro-ampere leaking current for v in to gnd when v in > 6v.
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 10/12 package outline drawing sot-23-5 o 2 symbpls min. nom. max. a 1.05 1.20 1.35 a1 0.05 0.10 0.15 a2 1.00 1.10 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 2.90 3.00 e 2.60 2.80 3.00 e1 1.50 1.60 1.70 e 0.95 bsc e1 1.90 bsc l 0.30 0.45 0.55 l1 0.60 ref 0 5 10 2 6 8 10 unit: mm
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 11/12 revision history revision date description 0.1 2011.01.06 original 1.0 2011.02.23 1. skip ?preliminary? 2. revise page3 ?fig.1? 3. revise page4 ?elect rical characteristics?
esmt/emp emp8040 elite semiconductor memory technology inc./elite micropower inc. publication date : feb. 2011 revision : 1.0 12/12 important notice all rights reserved. no part of this document may be repr oduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this docume nt are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is pr esented only as a guide or examples for the application of our products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellect ual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted un der any patents, copyrights or other intellectual property righ ts of esmt or others. any semiconductor devices may have in herently a certain rate of failure. to minimize risks associated with cu stomer's application, adequate design and operating safeguards against inju ry, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

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